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F72569
ACPI Controller IC for AMD K8/AM2 Platform
Release Date: Oct, 2006 Version: 0.26P
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Feature Integration Technology Inc.
F72569 F72569 Datasheet Revision History
Version 0.20P 0.21P
Date Dec, 2005 Apr, 2006
Page Preliminary version Model name modification Re-compose
Revision History
0.22P
May, 2006
1 14 23
Delete the description about Vref for overclock Description of linear controller correction Application circuit correction Delete the description about Vref in general description Add over current protection description Pin description Application circuit correction Application circuit correction
0.23P 0.24P 0.25P 0.26P
June, 2006 Aug, 2006 Sep,2006 Oct, 2006
1 11 3 20 20
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from such improper use or sales.
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F72569 Table of Contents
1 2 3 4 5 6 7 8
GENERAL DESCRIPTION ........................................................................................................................................................ 1 FEATURE ..................................................................................................................................................................................... 1 PIN CONFIGURATION .............................................................................................................................................................. 2 PIN DESCRIPTION..................................................................................................................................................................... 2 ELECTRICAL CHARACTERISTIC......................................................................................................................................... 6 BLOCK DIAGRAM ..................................................................................................................................................................... 8 SIMPLIFIED POWER SYSTEM DIAGRAM .......................................................................................................................... 9 FUNCTIONAL DESCRIPTION ................................................................................................................................................. 9 8.1 8.2 8.3 8.4 8.5 8.6 ACPI STATE .............................................................................................................................................................................. 9 CHARGE PUMP ........................................................................................................................................................................ 10 SOFT-START ............................................................................................................................................................................ 10 REFERENCE VOLTAGE ............................................................................................................................................................. 10 OVER-CURRENT PROTECTION................................................................................................................................................. 11 ACCESS INTERFACE ................................................................................................................................................................ 11
9
REGISTER DESCRIPTION ..................................................................................................................................................... 13 9.1 Register Index 01h .............................................................................................................................................................. 13 9.2 PWM_VRAM_11, PWM_VRAM_10 Fine Tune Voltage Register Index 02h ................................................................. 13 PWM_VTT_10, PWM_VTT_11 Fine Tune Voltage Register Index 04h.......................................................................... 14 LR_VDDA_10, LR_VDDA_11 Fine Tune Voltage Register Index 06h ........................................................................... 14 LRVLDT_10, LRVLDT_11 Fine Tune Voltage Register Index 08h ................................................................................. 15 LRVDDA, LRVLDT Fine Tune Voltage Register Index 09h ............................................................................................ 15 LED ACPI Frequency setting Register Index 0Ah .......................................................................................................... 16 PLED ACPI Frequency setting Register Index 0Bh ........................................................................................................ 16 SLED ACPI Frequency setting Register Index 0Ch ........................................................................................................ 17 Under Voltage, Over Current Enable Protection Register Index 10h............................................................................... 17 Register Index 11h ........................................................................................................................................................... 17 9.3 Register Index 03h .............................................................................................................................................................. 13 9.4 9.5 Register Index 05h .............................................................................................................................................................. 14 9.6 9.7 Register Index 07h .............................................................................................................................................................. 15 9.8 9.9 9.10 9.11 9.12 9.13 9.14
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9.15 Register Index 12h........................................................................................................................................................... 17
10 ORDERING INFORMATION .................................................................................................................................................. 18 11 PACKAGE DIMENSIONS (48LQFP)...................................................................................................................................... 19 12 APPLICATION CIRCUIT ........................................................................................................................................................ 20
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1 General Description
The F72569 is a fully compliant ACPI controller IC specific for AMD K8 CPU platform. The chip is used with an ATX power supply, and it integrates synchronous PWM controllers, regulators, several linear controllers, switching signals, monitoring and control function into a 48 pin LQFP package. Its operation mode (sleep or active) is selectable through some control signals. The F72569 provides 3 switch signals which can provide 5VDUAL, 5VUSB & 3.3VDUAL etc. The F72569 can also provide 5 linear regulators for system requirements. This chip integrates a charge pump engine to provide higher driving voltage for appropriate gate during standby. Besides, this chip offers current limiting that protects each PWM outputs, and provides soft-start for a linear regulator to avoid rush current. The power LED is programmable and compliant with PC2001. Moreover, this high-performance chip integrates I2C interface and provides adjustable linear controllers mechanism for dynamic over/under-voltage use. This chip is in a 48pin LQFP package and powered by 5VSB.
2 Feature
Compliant with AMD K8 timing sequence Provide 3 switching controlled signals for 5VDUAL, 5VUSB and 3.3VDUAL Programmable 5VDUAL/5VSTR/5VCC for USB device wake up Provide 5 linear controller and typically use for - -- 1 channel for DUAL3V power -- 1 channel for VDDA power -- 1 channel for VLDT power -- 2 channels for 0.8~5V voltage requirement Provide one PWM controller for DDR VDDQ Provide one PWM regulator for chipset power requirement 1 PWROK input signal(typically from ATXPWOKIN) and 1 PWROK output signal Provide resume reset signal(RSMRST#) Programmable power LED control Provide VREF and VSB9V voltage for generating different voltage use Power up soft-start and under-voltage monitoring for the linear regulators Over current protection(OCP) on PWM controller and under-voltage monitoring of all linear regulators Integrate I2C interface 48 pin LQFP package and 5VSB operation
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3 Pin Configuration
4 Pin Description
I/O12t I/O12ts I/OD16 OUT12 OD12 OD16 OD24 O24V4 INt INts AIN AOUT P - TTL level bi-directional pin with 12 mA source-sink capability - TTL level and schmitt trigger - TTL level bi-directional pin. Open-drain output with 16 mA sink capability - Output pin with 12 mA source-sink capability - Open-drain output pin with 12 mA sink capability - Open-drain output pin with 16 mA sink capability - Open-drain output pin with 24 mA sink capability - Output pin with 24mA driving capability, output 4V - TTL level input pin - TTL level input pin and schmitt trigger - Input pin(Analog) - Output pin(Analog) - Power
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Power Pins
PIN NO 8 12 21 30 32 42 45 18 PIN NAME GND VSB5V GND GND VSB5V GND VCC3V P Power pins TYPE
Feature Integration Technology Inc.
F72569
DESCRIPTION
VRAM_UGATE and VRAM_LGATE signal power, recommend to connect to VCC_PWM Vcc12V
Reset & Power Good & Control signal
PIN NO 1 2 3 10 11 PIN NAME PS_ONIN# PS_ONOUT# S5# VCORE_EN VCORE_GD TYPE INts OD12 INts OD12 INts PWR VSB5V VSB5V VSB5V chipset S5# signal. VSB5V VSB5V This pin is the open drain output to control CPU Vcore power enabled signal. This pin is the CPU Vcore power ready signal input. As VSB arrives at 3.3V, this pin will generate RSMRST# signal output after 43 RSMRST# OD12 VSB5V 66ms. Power Good output signal. Enable adjustable power signal. Error input signal for power off. Power Good Schmitt Trigger input signal. Typically, connected to ATX power 48 PWOKIN INts VSB5V Good. DESCRIPTION Normal power control signal input. Power control signal output. Connected to ATX power ON/OFF pin, normally. A low active ACPI control signal governs the S5 state. Typically, connected to
44 46 47
PWOK TURBO# FAULT#
OD16 INts INts
VSB5V VSB5V VSB5V
Switching Signal & Linear/PWM Controller
PIN NO 13 14 15 PIN NAME VTT_PWM VTT_FB COMP TYPE OUT5 AIN AOUT PWR VSB5V VSB5V VSB5V the PWM controller. DESCRIPTION External buffer PWM control output signal External buffer PWM feedback signal Output of the error amplifier used to compensate the feedback loop of
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16 17 19 20 22 24 VRAM_FB VRAM_OPS VRAM_LGATE VRAM_UGATE VTT_OPS VLDT_SEN AIN AOUT/AIN O O AOUT/AIN AIN VSB5V VSB5V VCC_PWM VCC_PWM VSB9V VSB5V
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F72569
VRAM PWM feedback signal VRAM PWM current protection signal VRAM PWM low gate control signal VRAM PWM up gate control signal External buffer PWM current protection signal Sense the voltage of the linear regulator. VLDT_SEN and VLDT_DRV act as a linear regulator and generate voltage for S0 state power. Connect this pin to the gate of a suitable N-channel MOSFET. 25 VLDT_DRV AOUT VSB9V VLDT_SEN and VLDT_DRV act as a linear regulator and generate voltage for S0 state power. Connect this pin to the gate of a suitable N-channel MOSFET. 26 VDDA_DRV AOUT VSB9V VDDA_SEN and VDDA_DRV act as a linear regulator and generate voltage and generate voltage for S0 sate power. Sense the voltage of the linear regulator. VDDA_SEN and VDDA_DRV 27 VDDA_SEN AIN VSB5V act as a linear regulator and generate voltage and generate voltage for S0 sate power. Sense the voltage of the linear regulator. LR1_SEN and LR1_DRV act 33 LR1_SEN AIN VSB5V as a linear regulator and generate voltage for standby or STR power. The default is for standby power. If VIN is main power, it can generate voltage for S0 sate power. Connect this pin to the gate of a suitable N-channel MOSFET. 34 LR1_DRV AOUT VSB9V LR1_SEN and LR1_DRV act as a linear regulator and generate voltage for standby or STR power. The default is for standby power. If VIN is main power, it can generate voltage for S0 sate power. Connect this pin to the gate of a suitable N-channel MOSFET. LR2_SEN and LR2_DRV act as a linear regulator and generate voltage 35 LR2_DRV AOUT VSB9V for standby or STR power. The default is for standby power. If VIN is main power, it can generate voltage for S0 sate power. Sense the voltage of the linear regulator. LR2_SEN and LR2_DRV act 36 LR2_SEN AIN VSB5V as a linear regulator and generate voltage for standby or STR power. The default is for standby power. If VIN is main power, it can generate voltage for S0 sate power. Sense the voltage of the linear regulator. VDUAL3V_SEN and 37 DAUL3V_SEN AIN VSB5V VDUAL3V_DRV act as an adjustable linear regulator and this regulator is typically incorporated with VCCGATE to generate dual voltage. Connect this pin to the gate of a suitable N-channel MOSFET. 38 DUAL3V_DRV AOUT VSB9V VDUAL3V_SEN and VDUAL3V_DRV act as an adjustable linear regulator and this regulator is typically incorporated with VCCGATE to
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generate dual voltage. Connect this pin to the gate of a suitable N-channel MOSFET. Generate dual 3.3V voltage with VDUAL3V_DRV and 39 VCCGATE AOUT VSB9V VDUAL3V_SEN. Generate USB voltage with USBGATE. Generate dual 5V voltage with DUALGATE. Connect this pin to the gate of a suitable N-channel MOSFET. 40 USBGATE AOUT VSB9V Generate USB voltage with VCCGATE. Connect this pin to the gate of a suitable N-channel MOSFET. 41 DUALGATE AOUT VSB9V Generate dual 5V voltage with VCCGATE.
Charge Pump
PIN NO 28 29 31 PIN NAME CP C2 C1 TYPE P AOUT AOUT PWR VSB9V capacitor. VSB9V power output. VSB9V VSB5V between C1 and C2 Positive end of charge pump capacitor Negative end of charge pump capacitor. Connect a 1uF ceramic capacitor DESCRIPTION Charge pump output (9V nominal). Decouple this pin with 1uF ceramic
Power LED
PIN NO 6 7 PIN NAME PLED SLED TYPE OD24 OD24 PWR VSB5V VSB5V DESCRIPTION Power LED. Can be programmed by setting register Suspend LED. Can be programmed by setting register
Others
PIN NO 4 5 9 23 PIN NAME SCLK SDATA VREF SS TYPE INts I/OD12ts AOUT AIN PWR VSB5V VSB5V VSB5V VSB5V soft-start rate. The value of capacitor is bigger, and the slew rate is slower. DESCRIPTION I2C serial bus clock I2C serial bus data Provide 1.25V reference voltage Soft-Start. Connect this pin to a small ceramic capacitor to determine the
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5 Electrical Characteristic
Absolute Maximum Ratings PARAMETER IC supply voltage ESD classification Maximum junction temperature (plastic package) Maximum storage temperature Maximum lead temperature (soldering 10s) SYMBOL VCC HBM Tj TSTO RATINGS UNIT V kV C C C
Note: If ICs are stressed beyond the limits listed in the "absolute maximum ratings", they may be permanently destroyed. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
DC and AC electrical characteristics (VCC = 12V, TA = 25C) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
VCC SUPPLY CURRENT/Regulated Voltage Nominal supply current 5VCC POWER-ON RESET Rising VCC threshold Falling VCC threshold OSCILLATOR AND Soft-start Free running frequency Ramp Amplitude Soft-start interval Dead time REFERENCE VOLTAGE Reference voltage PWM CONTROLLER GATE DRIVERS Upper Drive Source Upper Drive Sink Lower Drive Source Lower Drive Sink RUGATE RUGATE RLGATE RLGATE VDS = 1V, VGS = 12V, VDS = 1V, VGS = 12V VDS = 1V, VGS = 12V VDS = 1V, VGS = 12V 7 5 7 5 14 10 14 10 VREF VCC=5V, T= 25 0.784 0.8 0.816 V FOSC VOSC TSS TDT Css=0.1u 2V to 2V 8.4 20 200 250 1.5 12.4 30 17.4 50 300 kHz VP-P ms ns 3.0 2.7 3.3 3.0 3.6 3.3 V V ICC UGATE, LGATE and DRIVE2 open 6 15 mA
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PARAMETER Error Amplifier Slew Rate DC Gain Linear Regulator DC Gain Gain Bandwidth Product Slew Rate Drive High Output Voltage Drive Low Output Voltage Drive High Output Source Current Drive Low Output Sink Current Protection OCSET Current Source FB Under Voltage Trip VRAM(VDDQ) UV Level VTT_PWM (VGMCH) UV Level Charge Pump
Charge Pump Frequency Charge Pump Voltage
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F72569
SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
SR A0
4.5 34
V/us dB
70 1.86 38 12 0 Vo=9V; VDDA=10V Vo=1V; VDDA=10V 0.52 -0.54
dB MHz V/us V V mA mA
IOCSET FB Falling 0.4 0.4 0.4
40 0.5 0.5 0.5 0.6 0.6 0.6
uA V V V
250 9.5
KHz V
Switch Controller
DUALGATE Output High Voltage
9.5 10.8 10.8 12 12 13.2 13.2
V V V
VCCGATE Output High Voltage USBGATE SS Source Current
: Design Guarantee
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6 Block Diagram
PLED SLED S5# SS 1.25VREF SCLK SDATA VSB5V VCC3V VTT_PWM VTT_COMP VTT_OPS VTT_FB VRAM_UGATE VRAM_LGATE VRAM_OPS VRAM_FB LR1_DRV LR1_SEN LR2_DRV LR2_SEN
PWOK PWOKIN FAULT# TURBO# PS_ONIN# PS_ONOUT# RSMRST# VCORE_EN VCORE_GD
VREF Control Logic
I2C Interface
VTT PWM Regulator VRAM PWM Controller
F72569DG
DUAL3V_DRV DUAL3V_SEN
Linear Controller 1 Linear Controller 2
3VDUAL LR Controller 5VDUAL 5VUSB
LR3_SEN
VCCGATE USBGATE DUALGATE
VLDT LR Controller
VDDA LR Controller
Charge Pump
C1 C2
GND
LR3_DRV VDDA_DRV VDDA_SEN CP
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7 Simplified Power System Diagram
VCORE 12V
Multi-Phase PWM
VCORE_GD
MOSFET Driver
AMD CPU
VCORE_EN
VDDA (2.5V/200mA)
VLDT (1.2V) 5VSB 3V
PCIE x 16
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VTT_PWM
Chipset
MOSFET Driver
PCIE x 1
PCIE_PWR(1.5V) USB_DUAL(5V)
USB Device Other Device
DUAL_3V
ATX Power
VRAM_UGATE
VDDQ
VRAM_LGATE DUAL_5V 2.5V/1.8V
DRAM
8 Functional Description
8.1 ACPI state
The Advanced Configuration and Power Interface (ACPI) is a system for controlling the usage of power in a computer. It lets computer manufacturers and users to determine the power usage of computer dynamically. There are three ACPI states that are of primary concern to the system designer and they are designated S0, S3 and S5. S0 is a full-power state and the computer is being actively used in this state. The other two are called sleep states and reflect different power consumption when power-down. S3 is a state the processor is powered down but the last state is being stored in memory which is still active. S5 is a state that memory is off and the last state of the
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processor has been stored to the hard disk. Take S3 and S5 as a comparison, the computer can come back more quickly to full-power state in S3 than S5 due to data restored from the memory is faster than from the hard disk. However, S5 draws the minimal power compared to S0 and S3 because of powering off the memory. It is anticipated that only the following state transitions may happen: S0/ S5. Among them, S3/ S3, it is necessary to come back to S0 first. The transition S5/ S3, S0/ S5, S5/ S0, S3/ S0 and S3/
S5 is an illegal transition and won't be allowed by state machine. In order to enter to S5 from S3 will occur only as an immediate state during
state transition from S5/ S0. It isn't allowed in the normal state transition.
8.2 Charge pump
The F72569 is incorporated with an embedded charge pump to provide higher driving voltage. Pin 29(CP) supports 10mA driving current and ensures 9V output voltage or above. In main operation, the VSB9V signals of the F72569 are run from the +12V supplied by ATX power which also supplies to other MOSFET gates. However, during standby state, the +12V will be off and it needs to provide power to the chip and the appropriate gates. Therefore, the F72567 is incorporated with a free running charge pump. As shown in the schematic, there is a capacitor connected between C1 and C2 of the F72569 act as a charge pump with internal diodes. There must be a serial diode in the 12V input to prevent back-feeding the charge pump to the +12V main in standby. It also needs a bypass capacitor connected with 12V input line to filter high-frequency noise.
8.3 Soft-start
SS of the F72569 acts as a soft-start function. As shown in the schematic, a ceramic capacitor is attached between this pin and the ground. When power is first applied to the chip, a constant current is applied from the pin into an external capacitor, linearly ramping up the voltage. This ramp in turn controls the internal reference of the F72569 which provides a soft-start for the linear regulator. Switches must be either on or off in the system to avoid the effect on them from the soft-start. It is important to know soft-start is not an enable signal, pulling it low will not be sure to turn off all outputs. If there are appropriate signals asserted, the switches will be turned on at once. The actual state of the F72569 in power up will be determined by the controlled input signal and the soft-start is effective only during power on.
8.4 Reference voltage
The pin10 (VREF) is an output pin that is driven by a small output buffer to provide the 1.25V reference voltage to other devices
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in the system.
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F72569
8.5 Over-current Protection
To sense the low-side MOSFET's RDS (ON) to set over-current trip point. Connecting a resistor (ROCSET) from this pin to PHASE to set the over-current trip point, ROCSET, an internal 40A current source, and the lower MOSFET on resistance, RDS (ON), sets the converter over-current trip point (IOCSET) according to the following equation:
8.6 Access interface
The F72569 can be connected to a compatible 2-wire serial system Management Bus (SMBus) as a slave device under the control of the master device, using two device terminals SCL and SDA. The controller can provide a clock signal to the device SCL pin and read/write data from/to the device through the device SDA pin. The default address is 0x5E(0101_1110) and the operation of the device to the bus is described with details in the following sections.
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(a) SMBus write to internal address register followed by the data byte
0 SCLK SDA
Start By Master
7
8
0
7
8
0
1
0
1
1
1
1
R/W
Ack by 569
D7
D6
D5
D4
D3
D2
D1
D0
Ack by 569
Frame 1 Serial Bus Address Byte 0
Frame 2 Internal Index Register Byte
7 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0
8
Frame 3 Data Byte
Stop by Master
Figure 1. Serial Bus Write to Internal Address Register followed by the Data Byte
(b) Serial bus write to internal address register only
0 SCL SDA
Start By Master
7
8
0
7
8
0
1
0
1
1
1
1
R/W
Ack by 569
D7
D6
D5
D4
D3
D2
D1
D0
Ack by 569 Stop by Master
Frame 1 Serial Bus Address Byte 0
Frame 2 Internal Index Register Byte
Figure 2. Serial Bus Write to Internal Address Register Only
(c) Serial bus read from a register with the internal address register prefer to desired location
0 SCL SDA
Start By Master
7
8
0
7
8
0
1
0
1
1
1
1
R/W
Ack by 569
D7
D6
D5
D4
D3
D2
D1
D0
Ack Stop by by Master Master
Frame 1 Serial Bus Address Byte 1
Frame 2 Internal Index Register Byte
Figure 3. Serial Bus Read from Internal Address Register
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9 Register Description
9.1 Register Index 01h
Reserved register. Do not write the reserved register to avoid the mis-action, please.
9.2
Bit
PWM_VRAM_11, PWM_VRAM_10 Fine Tune Voltage Register Index 02h
Name R/W Default Description According to Turbo hardware pin setting, to fine tune PWM_VRAM reference voltage. If Turbo = 1, the PWM_VRAM Voltage table is set by Register 02h bit 7:4. 0000 : 0.74V 1000 : 0.90V 0001 : 0.76V 1001 : 0.92V 0010 : 0.78V 1010 : 0.94V 0011 : 0.80V 1011 : 0.96V 0100 : 0.82V 1100 : 0.98V 0101 : 0.84V 1101 : 1.00V 0110 : 0.86V 1110 : 1.02V 0111 : 0.88V 1111 : 1.04V The function must be enable by Register 09 Bit3 and Register 0A bit 3 According to Turbo hardware pin setting to fine tune PWM_VRAM reference voltage. If Turbo = 0, the PWM_VRAM Voltage table is set by Register 02h bit 3:0. 0000 : 0.74V 1000 : 0.90V 0001 : 0.76V 1001 : 0.92V 0010 : 0.78V 1010 : 0.94V 0011 : 0.80V 1011 : 0.96V 0100 : 0.82V 1100 : 0.98V 0101 : 0.84V 1101 : 1.00V 0110 : 0.86V 1110 : 1.02V 0111 : 0.88V 1111 : 1.04V The function must be enable by Register 09 Bit3 and Register 0A bit 3
7:4
PWMVRAM_11
R/W
3
3:0
PWMVRAM_10
R/W
3
9.3
Register Index 03h
Reserved register. Do not write the reserved register to avoid the mis-action, please.
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9.4
Bit
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PWM_VTT_10, PWM_VTT_11 Fine Tune Voltage Register Index 04h
Name R/W Default Description
F72569
7:4
PWMVTT_11
R/W
3
3:0
PWMVTT_10
R/W
3
According to Turbo hardware pin setting to fine tune PWM_VTT reference voltage. If Turbo = 1, the PWM_VTT Voltage table is set by Register 04h bit 7:4. 0000 : 0.74V 1000 : 0.90V 0001 : 0.76V 1001 : 0.92V 0010 : 0.78V 1010 : 0.94V 0011 : 0.80V 1011 : 0.96V 0100 : 0.82V 1100 : 0.98V 0101 : 0.84V 1101 : 1.00V 0110 : 0.86V 1110 : 1.02V 0111 : 0.88V 1111 : 1.04V The function must be enable by Register 09 Bit3 and Register 0A bit 3 According to Turbo hardware pin setting to fine tune PWM_VTT reference voltage. If Turbo = 0, the PWM_VTT Voltage table is set by Register 04h bit 3:0 0000 : 0.74V 1000 : 0.90V 0001 : 0.76V 1001 : 0.92V 0010 : 0.78V 1010 : 0.94V 0011 : 0.80V 1011 : 0.96V 0100 : 0.82V 1100 : 0.98V 0101 : 0.84V 1101 : 1.00V 0110 : 0.86V 1110 : 1.02V 0111 : 0.88V 1111 : 1.04V The function must be enable by Register 09 Bit3 and Register 0A bit 3
9.5
Register Index 05h
Reserved register. Do not write the reserved register to avoid the mis-action, please.
9.6
Bit
LR_VDDA_10, LR_VDDA_11 Fine Tune Voltage Register Index 06h
Name R/W Default Description According to Turbo hardware pin setting to fine tune LR_VDDA reference voltage. If Turbo = 1, the LR_VDDA Voltage table is set by Register 06h bit 7:4. 0000 : 0.74V 1000 : 0.90V 0001 : 0.76V 1001 : 0.92V 0010 : 0.78V 1010 : 0.94V 0011 : 0.80V 1011 : 0.96V 0100 : 0.82V 1100 : 0.98V 0101 : 0.84V 1101 : 1.00V 0110 : 0.86V 1110 : 1.02V 0111 : 0.88V 1111 : 1.04V The function must be enable by Register 09 Bit3 and Register 0A bit 3
7:4
LRVDDA_11
R/W
3
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According to Turbo hardware pin setting to fine tune LR_VDDA reference voltage. If Turbo = 0, the LR_VDDA Voltage table is set by Register 06h bit 3:0 0000 : 0.74V 1000 : 0.90V 0001 : 0.76V 1001 : 0.92V 0010 : 0.78V 1010 : 0.94V 0011 : 0.80V 1011 : 0.96V 0100 : 0.82V 1100 : 0.98V 0101 : 0.84V 1101 : 1.00V 0110 : 0.86V 1110 : 1.02V 0111 : 0.88V 1111 : 1.04V The function must be enable by Register 09 Bit3 and Register 0A bit 3
3:0
LR_VDDA_10
R/W
3
9.7
Register Index 07h LRVLDT_10, LRVLDT_11 Fine Tune Voltage Register Index 08h
Name R/W Default Description According to Turbo hardware pin setting to fine tune LRVLDT reference voltage. If Turbo = 1, the LRVLDT Voltage table is set by Register 08h bit 7:4. 0000 : 0.74V 1000 : 0.90V 0001 : 0.76V 1001 : 0.92V 0010 : 0.78V 1010 : 0.94V 0011 : 0.80V 1011 : 0.96V 0100 : 0.82V 1100 : 0.98V 0101 : 0.84V 1101 : 1.00V 0110 : 0.86V 1110 : 1.02V 0111 : 0.88V 1111 : 1.04V The function must be enable by Register 09 Bit3 and Register 0A bit 3 According to Turbo hardware pin setting to fine tune LRVLDT reference voltage. If Turbo = 0, the LRVLDT Voltage table is set by Register 08h bit 3:0 0000 : 0.74V 1000 : 0.90V 0001 : 0.76V 1001 : 0.92V 0010 : 0.78V 1010 : 0.94V 0011 : 0.80V 1011 : 0.96V 0100 : 0.82V 1100 : 0.98V 0101 : 0.84V 1101 : 1.00V 0110 : 0.86V 1110 : 1.02V 0111 : 0.88V 1111 : 1.04V The function must be enable by Register 09 Bit3 and Register 0A bit 3
Reserved register. Do not write the reserved register to avoid the mis-action, please.
9.8
Bit
7:4
LRVLDT_11
R/W
3
3:0
LRVLDT_10
R/W
3
9.9
Bit 7-6 5 4 3
LRVDDA, LRVLDT Fine Tune Voltage Register Index 09h
Name USBMODE Reserved Reserved TURBO_EN R/W R/W R/W R/W R/W Default 1 1 0 0 Reserved Reserved TURBO function Enable, if set to 1 the register 01~08h will enable fine tune function when the fine tune setting is Turbo mode (Register 0A bit 3) Description USB Power mode select, 00:DUAL 01:STR 10:OFF 11:OFF
15
2006 V0.26P
Fintek
Feature Integration Technology Inc.
F72569
2 TURBO_INV R/W 0 TURBO function sequence inverter. TURBO_INV=0: If TURBO value changes from 0 to 1, it will fine tune directly, Otherwise, it will delay 20ms to fine tune reference voltage. TURBO_INV=1: If TURBO value changes from 1 to 0, it will fine tune directly. Otherwise, it will delay 20ms to fine tune reference voltage Reserved When register 09H bit 1 is set to FAULT_N mode, Set this bit to 1 to enable FAULT Function, When FAULT_N is low in S0 State, it will Shut down PWM_VRAM, PWM_VTT, LR_PCIE, LR_VID directly,.
1 0
Reserved FAULT_EN
R/W R/W
0 0
9.10
Bit 7-6
LED ACPI Frequency setting Register Index 0Ah
Name PLED_SET[9:8] R/W R/W Default 0 3 Description PLED frequency setting, When PLED_SET[9:8] set equal to S3_N, S5_N, the PLED pin will be tri-state (OD) *note : {1,1} represent S0 State, {0,1} represent S3 State, {00} represent S5 State, {1,0} the state is reserved SLED frequency setting, When SLED_SET[9:8] set equal to S3_N, S5_N, the PLED pin will be tri-state (OD) *note : {1,1} represent S0 State, {0,1} represent S3 State, {00} represent S5 State, {1,0} the state is reserved Manual mode or Turbo mode selection, 0:turbo 1:Manual If the setting is Turbo mode, set register 09H bit 3 to enable the fine tune function. If the setting is Manual mode, Write Register 02/04/06/08 Bit [7:4] to fine tune voltage. Set to 1 , the PLED and SLED CLK is inverted PWM_VRAM Over current enable PWM_VTT Over current enable
5-4
SLED_SET[9:8]
R/W
3
VFB_SEL
R/W
0
2 1 0
LED_INV VRAM_OCEN VTT_OCEN
R/W R/W R/W
1 1 1
9.11
Bit
PLED ACPI Frequency setting Register Index 0Bh
Name R/W Default Description PLED frequency setting, When the PLED_SET[7:6] = S3_N, S5_N, PLED will be 1HZ toggle pulse with 50 duty cycle PLED_SET[5:4] = S3_N, S5_N, PLED will be 1/2 HZ toggle pulse with 50 duty cycle PLED_SET[3:2] = S3_N, S5_N, PLED will be 1/4HZ toggle pulse with 50 duty cycle PLED_SET[1:0] = S3_N, S5_N, PLED will drive low *note : {1,1} represent S0 State, {0,1} represent S3 State, {00} represent S5 State, {1,0} the state is reserved
7-0
PLED_SET[7:0]
R/W
9B
16
2006 V0.26P
Fintek
9.12
Bit
Feature Integration Technology Inc.
SLED ACPI Frequency setting Register Index 0Ch
Name R/W Default Description
F72569
7-0
SLED_SET[7:0]
R/W
98
SLED frequency setting, When the SLED_SET[7:6] = S3_N, S5_N, SLED will be 1HZ toggle pulse with 50 duty cycle SLED_SET[5:4] = S3_N, S5_N, SLED will be 1/2 HZ toggle pulse with 50 duty cycle SLED_SET[3:2] = S3_N, S5_N, SLED will be 1/4HZ toggle pulse with 50 duty cycle SLED_SET[1:0] = S3_N, S5_N, SLED will drive low *note : {1,1} represent S0 State, {0,1} represent S3 State, {00} represent S5 State, {1,0} the state is reserved
9.13
Bit 7 6 5 4 3 2 1 0
Under Voltage, Over Current Enable Protection Register Index 10h
Name VDDA_UVEN VLDT_UVEN VDUAL3V_UVEN LR1_UVEN LR2_UVEN Reserved PWM_VTT_UVEN R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 1 1 1 1 1 VDDA Under voltage enable VLDT Under voltage enable VDUAL3V Under voltage enable LR1 Under voltage enable LR2 Under voltage enable Reserved PWM_VTT Under voltage enable PWM_VRAM Under voltage enable Description
PWM_VRAM_UVEN R/W
9.14
Bit 7 6 5 4 3 2
Register Index 11h
Name DUAL[1:0] Delay[1:0] Reserved Reserved R/W R/W R/W R/W R/W R/W R/W Default 0 1 1 1 0 0 0 Reserved Reserved Reserved Function: when set to 1, it can decrease regulators VFB voltage, it must fix the related fine tune register bit2, bit 3 to zero, for example 100XX, It provide 4 kinds decrease voltage 10000 : 0.72V 10001 : 0.70V 10010 : 0.68V 10011 : 0.66V Set to 1 can toggle S5_N to recovery, if VRAM, VTT, LR_PCIE, LR_VID Shut down by Over current or Under voltage or Fault_N SD , Set to 0, must power off to recovery. Description DUAL3V selection 00:3.21V, 01 : 3.3V, 10 :3.38V, 11: 3.456v, V3VOK delay timer, 00: 100ms, 01: 200ms, 10 : 300ms, 11 : 400ms
1
DEC_VFB
R/W
0 0 PROTECTION_SEL R/W
9.15
Bit 7
Register Index 12h
Name R/W Default 0 Description If Register 12H bit 4 set to 1, write this bit to1 can set PSON_OUT to high. PROG_PSN_OUT_S R/W ET
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2006 V0.26P
Fintek
6 5 4 3 2 1 0 SAME_UV PSON_OUT_UV SOFT_PSON_OUT Reserved Reserved Reserved Reserved R/W R/W R/W R/W R/W R/W R/W 1 0 0 0 0 0 0
Feature Integration Technology Inc.
F72569
Set to 1 will Set the VRAM, VDDA, VTT, VLDT Shut down when each power occurs fault event Set to 1 will Set the PSON_OUT to high when VRAM, VDDA, VTT, VLDT power fault event occurs Set to 1 can program PSON_OUT to HIGH Reserved Reserved Reserved Reserved
10 Ordering Information
Part Number F72569DG Package Type 48-LQFP (Green Package) Production Flow Commercial, 0C to +70C
18
2006 V0.26P
Fintek
Feature Integration Technology Inc.
F72569
11 Package Dimensions (48LQFP)
HD D
36 25
Dimension in inch
Dimension in mm Min.
--0.05 1.35 0.17 0.09
Symbol
Min.
Nom.
Max.
Nom.
----1.40 0.20 --7.00 7.00 0.50 9.00 9.00
Max.
1.60 0.15 1.45 0.27 0.20
37
24
E
HE
48
13
1
e
b
12
A A1 A2 b c D E e HD HE L L1 y 0
Notes:
c
0.45
0.60 1.00
0.75
--0
0.08 3.5
--7
A2
A
Seating Plane
See Detail F
A1 y
L L1 Detail F
1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec.
Feature Integration Technology Inc.
Headquaters 7F, No 31, Shintai Rd., Jubei City, Hsinchu 302, Taiwan, R.O.C. TEL : 886-3-6562727 FAX : 886-3-6560537 www: http://www.fintek.com.tw
Taipei Office Bldg. K4, 7F, No.700, Jungjeng Rd., Junghe City, Taipei, Taiwan 235, R.O.C. TEL : 866-2-8227-8027 FAX : 866-2-8227-8037
Please note that all datasheet and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this datasheet belong to their respective owner
19
2006 V0.26P
Fintek 12 Application Circuit
Feature Integration Technology Inc.
F72569
VBS5V VCC12V VSB5V R2 4.7k PS_ON PS_ON# C6 1u U1 11 12 13 14 15 16 17 18 19 20 3.3V -12V COM PS_ON COM COM COM -5V 5V 5V ATX 3.3V 3.3V COM 5V COM 5V COM PWR_OK 5VSB 12V 1 2 3 4 5 6 7 8 9 10 C2 470u VCC12V VSB5V PWROK C11 470u C9 C10 470u 1u U2 C1 470u C3 1u C5 LR2_SEN LR2_DRV LR1_DRV LR1_SEN 1u VDDA_SEN VDDA_DRV VLDT_DRV D2 VCC3V VCC5V R1 2.2 D1 MOSFET_EN_GDS Q1 USBGATE VCCGATE Q2 MOSFET_EN_GDS USB C7 220u C8 220u MOSFET_EN_GDS Q3 DUALGATE VSB5V VCC5V VSB5V VCC5V VCCGATE
Q4
Q5
C4 1u
DUAL5V
USB
DUAL5V
DUAL3V
R3 4.7k VCC3V L1 1u C13 1u C14 470u*2 VCC12V R9 R8 4.7k 10K R11
DUAL5V
RSMRST# PWOK C18 TURBO# FAULT# VCC3V VCC5V VCC3V R15 R18 R21 4.7k
VDUAL3V_SEN VDUAL3V_DRV VCCGATE USBGATE DUALGATE
LR2_SEN LR2_DRV LR1_DRV LR1_SEN VSB5V C1 GND C2 CP VDDA_SEN VDDA_DRV VLDT_DRV
ATX power connector
36 35 34 33 32 31 30 29 28 27 26 25
R10 2.2 VRAM_UGATE VRAM_OPS R12 20k
Q6 MOSFET_EN_GDS VRAM L2 4.7u C21 1u C22 470u*2
PS_ONIN# PS_ONOUT# S5# SCLK SDATA PLED SLED GND VREF VCORE_EN VCORE_GD VSB5V
1u
37 38 39 40 41 42 43 44 45 46 47 48
VDUAL3V_SEN VDUAL3V_DRV VCCGATE USBGATE DUALGATE GND RSMRST# PWOK VCC3V TURBO# FAULT# PWOKIN
F72569
VLDT_SEN SS VTT_OPS GND VRAM_UGATE VRAM_LGATE VCC_PWM VRAM_OPS VRAM_FB COMP VTT_FB VTT_PWM
24 23 22 21 20 19 18 17 16 15 14 13
VLDT_SEN VTT_OPS
C12 0.1u Vsb/Vcc/Vdual VDDA_DRV R4 6.8k C19 470p VDDA_SEN R5 2.2 C15 220u Q7 MOSFET_EN_GDS VDDA R16 R C23 220u VLDT_DRV R6 6.8k C20 470p VLDT_SEN R7 2.2 C16 220u Q8 MOSFET_EN_GDS VLDT R17 R C24 220u Vsb/Vcc/Vdual
VRAM_UGATE VRAM_LGATE VRAM_OPS VRAM_FB COMP VTT_FB VTT_PWM C17 1u
R13
R
R14
R
Q9 MOSFET_EN_GDS VRAM_LGATE R19 2.2 VRAM_FB
3.9K
D3 SCHOTTKY
4.7k PWROK 4.7k R22 VSB5V PSON_IN# S5# R28 VCC5V R29 VSB5V 330 330 4.7k
1 2 3 4 5 6 7 8 9 10 11 12
R24 R25 R
R
R20 4.7k
R23
2.2 VSB5V VCC3V
VDDA
VLDT
PS_ON# C26 D4 D5 1u C27 1u R26 4.7k R27 4.7k
C25 10n SCLK SDATA
VRAM
VCORE_GD VCORE_EN Vsb/Vcc/Vdual LR1_DRV LR2_DRV R31 2.2 C28 220u Q10 MOSFET_EN_GDS LR1 R37 R C37 220u R32 6.8k C35 470p LR2_SEN R33 2.2 C29 220u Q11 MOSFET_EN_GDS LR2 R38 R C38 220u Vsb/Vcc/Vdual
VCC5V C30 C33 0.1u 1u R34 2.2
L3
1u C31 1u
VCC12V C32 470u*2
R30 6.8k VSB5V C36 VTT 220u VDUAL3V_DRV C40 470u*2 VDUAL3A_SEN C41 Q13 MOSFET_EN_GDS VCCGATE Q14 MOSFET_EN_GDS DUAL3V VCC3V C34 470p LR1_SEN
U3 1 2 3 4 UGATE BOOT PWM GND PHASE PVCC VCC LGATE 8 7 6 5 R40 20k C42 1u COMP C44 1.2n R44 10.7k C45 47n VTT_FB
Q12 MOSFET_EN_GDS L4 4.7u C39 D6 SCHOTTKY 1u
R35
R
R36
R
VTT_PWM
HIP6601 VTT_OPS
Q15 MOSFET_EN_GDS R39 2.2
LR1
LR2
R41 R42 R R43 10
R
DUAL3V
C43 47n
1000u
Title
VTT
ACPI controller for AMD
Size Document Number Custom
F72569
Rev 0.4 Sheet 1 of 1
Date:
Friday , September 15, 2006
20
2006 V0.26P

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